Geometry Accelerator Features And Functions; High-Speed Graphics Dma Engine; Mimd Dsp Architecture; Sequence Controller - Intergraph RealiZm Graphics Z10 Hardware User's Manual

Geometry Accelerator Features and Functions

The Geometry Accelerator available for use with Z13, Z25, and V25 employs the following
features and functions to accelerate the geometry processing requirements of computer
graphics.
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High-speed graphics DMA engine

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MIMD DSP architecture

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Sequence Controller

High-Speed Graphics DMA Engine
The Geometry Accelerator uses high-speed DMA engines to accelerate PCI bus data transfers.
An independent DMA engine transfers data in bursts and frees the host processor from
transferring massive amounts of graphics data over the PCI bus.
MIMD DSP Architecture
The Geometry Accelerator features a multiple instruction multiple data (MIMD) architecture
to harness the power of six floating-point digital signal processors (DSPs) operating in
parallel. The DSPs speed the compute-intensive geometry calculations of 3D graphics. Each
DSP can execute 120 million floating point operations per second (MFLOPS), and contains
10 DMA engines to ensure nonstop data flow to the Sequence Controller.
Sequence Controller
To achieve maximum efficiency in a MIMD architecture, multiple processors operate
independently on multiple data sets. The six Geometry Accelerator DSPs process graphics
requests in turn and may generate output requests in a different order than the input requests.
The Sequence Controller places the output requests into the proper time sequence.
The PCI bus is a high-performance bus capable of operating up to 33 MHz. The Geometry
Accelerator is a 32-bit PCI bus peripheral with bus mastership capability, which uses the PCI
bus to transfer data from the host processor.
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