Deeper Sleep Vcc And Icc Loadline For Low-Voltage, Ultra-Low-Voltage And Power Optimized Performance Processor - Intel P8700 - Core 2 Duo Processor Datasheet

Electrical Specifications
Figure 8. Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and
Power Optimized Performance Processor
V
CC-CORE
V
CC-CORE, DC
V
CC-CORE
NOTES:
1. Applies to Low-Voltage, Ultra-Low-Voltage and Power Optimised Performance processors in
22 mmx22 mm package.
2. Deeper Sleep mode tolerance depends on VID value.
Datasheet
V
CC-CORE
Slope = -4.0 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
max {HFM|LFM}
max {HFM|LFM}
V nom
CC-CORE
{HFM|LFM}
V min
CC-CORE, DC
{HFM|LFM}
+/-V Tolerance
min {HFM|LFM}
CC-CORE
= VR St. Pt. Error 1/
0
Note 1/ V Set Point Error Tolerance is per below :
CC- CORE
Tolerance V
CC- CORE
--------------- --------------------------------------------------------
+/-[(VID*1.5%)-3mV]
+/-(11.5mV-3mV)
Total tolerance window
including ripple is +/-35mV for C6
[V]
10mV= RIPPLE
VID Voltage Range
V > 0.7500V
CC- CORE
0.5000V </= V
0.3000V </= V
I
CC-CORE
[A]
I max
CC-CORE
{HFM|LFM}
</= 0.7500V
CC- CORE
< 0.5000V
CC- CORE
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