Intel P8700 - Core 2 Duo Processor Datasheet page 76

Core 2 duo mobile processor, intel core 2 solo mobile processor and intel core 2 extreme mobile processor on 45-nm process, platforms based on mobile intel 4 series express chipset family
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Table 17.
Pin #
Pin Name
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
G2
G3
G4
G5
G6
G21
G22
G23
G24
76
Pin # Listing
Signal Buffer
Type
VSS
Power/Other
RS[0]#
Common Clock
RS[1]#
Common Clock
VSS
Power/Other
RSVD
Reserved
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
DRDY#
Common Clock
VSS
Power/Other
D[4]#
Source Synch
D[1]#
Source Synch
VSS
Power/Other
D[13]#
Source Synch
VSS
Power/Other
TRDY#
Common Clock
RS[2]#
Common Clock
VSS
Power/Other
BPRI#
Common Clock
HIT#
Common Clock
VCCP
Power/Other
D[3]#
Source Synch
VSS
Power/Other
D[9]#
Source Synch
Package Mechanical Specifications and Pin Information
Table 17.
Directi
Pin #
Pin Name
on
G25
D[5]#
Input
G26
Input
H1
ADS#
H2
REQ[1]#
H3
H4
LOCK#
H5
DEFER#
H6
H21
H22
D[12]#
H23
D[15]#
H24
H25
DINV[0]#
DSTBP[0]
H26
Input/
Output
J1
A[9]#
J2
Input/
Output
J3
REQ[3]#
Input/
Output
J4
A[3]#
J5
Input/
Output
J6
J21
Input
J22
Input
J23
D[11]#
Input
J24
D[10]#
Input/
J25
Output
DSTBN[0]
J26
Input/
K1
Output
K2
REQ[2]#
Input/
Output
Pin # Listing
Signal Buffer
Type
Source Synch
VSS
Power/Other
Common Clock
Source Synch
VSS
Power/Other
Common Clock
Common Clock
VSS
Power/Other
VSS
Power/Other
Source Synch
Source Synch
VSS
Power/Other
Source Synch
Source Synch
#
Source Synch
VSS
Power/Other
Source Synch
Source Synch
VSS
Power/Other
VCCP
Power/Other
VCCP
Power/Other
VSS
Power/Other
Source Synch
Source Synch
VSS
Power/Other
Source Synch
#
VSS
Power/Other
Source Synch
Datasheet
Directi
on
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output

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