Table of Contents
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5.1.3
Digital Thermal Sensor .......................................................................... 111
5.2
Out of Specification Detection............................................................................ 112
5.3
PROCHOT# Signal Pin ...................................................................................... 112
Figures
1
Core Low-Power States .............................................................................................12
2
Package Low-Power States ........................................................................................13
3
Dynamic FSB Frequency Switching Protocol..................................................................22
4
Extreme Edition Processors ........................................................................................43
5
Core Extreme Edition Processors ................................................................................44
6
7
Performance Processor ..............................................................................................46
8
Performance Processor ..............................................................................................47
9
6-MB and 3-MB on 6-MB Die Micro-FCPGA Package Drawing (Sheet 1 of 2) ......................52
10
3-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ...................................53
11
3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)...................................54
12
3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ..................................55
13
3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ..................................56
14
Drawing ..................................................................................................................57
15
Drawing ..................................................................................................................58
16
Processor Pinout (Top Package View, Left Side) ............................................................59
17
Processor Pinout (Top Package View, Right Side) ..........................................................60
18
Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side .....................80
19
Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side ...................81
20
Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side .....................82
21
Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side ...................83
Tables
1
Coordination of Core Low-Power States at the Package Level..........................................13
2
Voltage Identification Definition ..................................................................................26
3
BSEL[2:0] Encoding for BCLK Frequency......................................................................29
4
FSB Pin Groups ........................................................................................................30
5
Processor Absolute Maximum Ratings..........................................................................31
6
7
8
(25 W) in Standard Package ......................................................................................35
9
SFF Processors.........................................................................................................37
10
11
12
(5.5 W) SFF Processor...............................................................................................41
13
AGTL+ Signal Group DC Specifications ........................................................................48
14
CMOS Signal Group DC Specifications..........................................................................49
15
Open Drain Signal Group DC Specifications ..................................................................49
4
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