Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 26

a) RSM from a C-state SMI during an MWAIT instruction.
b) RSM from an SMI during a HLT instruction.
Implication: There may be a smaller than expected value in the INST_RETIRED
performance monitoring counter. The extent to which this value is smaller
than expected is determined by the frequency of the above cases.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK16. Performance Monitoring Event For Number Of Reference Cycles When
The Processor Is Not Halted (3CH) Does Not Count According To The
Specification
The CPU_CLK_UNHALTED performance monitor with mask 1 counts bus clock
Problem:
cycles instead of counting the core clock cycles at the maximum possible
ratio. The maximum possible ratio is computed by dividing the maximum
possible core frequency by the bus frequency.
Implication: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value
lower than expected. The value is lower by exactly one multiple of the
maximum possible ratio.
Workaround: Multiply the performance monitor value by the maximum possible ratio.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK17. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
An external A20M# pin if enabled forces address bit 20 to be masked (forced
Problem:
to zero) to emulates real-address mode address wraparound at 1 megabyte.
However, if all of the following conditions are met, address bit 20 may not be
masked.
Paging is enabled
•
• A linear address has bit 20 set
The address references a large page
•
A20M# is enabled
•
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been
observed with any commercially available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of
address bit 20 could be applied to an address that references a large page.
A20M# is normally only used with the first megabyte of memory.
For the steppings affected, see the Summary Tables of Changes.
Status:
26
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Intel Core™2 Extreme Quad-Core Processor QX6000
Sequence and Intel ® Core™2 Quad Processor Q6000
Errata
Δ
Δ Sequence
Specification Update