Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 49

Errata
Implication: Software that uses WB to WT memory aliasing may violate proper store
ordering.
Workaround: Do not use WB to WT aliasing.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK82. A MOV Instruction from CR8 Register with 16 Bit Operand Size
Will Leave Bits 63:16 of the Destination Register Unmodified
Moves to/from control registers are supposed to ignore REW.W and the 66H
Problem:
(operand size) prefix. In systems supporting Intel
when the processor is operating in VMX non-root operation and "use TPR
shadow" VM-execution control is set to 1, a MOV instruction from CR8 with a
16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and
leave bits 63:16 at the destination register unmodified, instead of
storing zeros in them.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK83. CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
CPUID leaf 0Ah reports the architectural performance monitoring version that
Problem:
is available in EAX[7:0]. Due to this erratum CPUID reports the supported
version as 2 instead of 1.
Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in
comparison to which features are actually supported.
Workaround: Software should use the recommended enumeration mechanism described in
the Architectural Performance Monitoring section of the Intel
Architectures Software Developer's Manual, Volume 3: System Programming
Guide.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK84. Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
In certain circumstances, when a floating point exception (#MF) is pending
Problem:
during single-step execution, processing of the single-step debug exception
(#DB) may be mishandled.
Implication: When this erratum occurs, #DB will be incorrectly handled as follows:
#DB is signaled before the pending higher priority #MF (Interrupt 16)
•
#DB is generated twice on the same instruction
•
Workaround: None identified.
Intel ® Core™2 Extreme Quad-Core Processor QX6000
Intel ® Core™2 Quad Processor Q6000
Specification Update
Δ Sequence and
Δ Sequence
®
Virtualization Technology,
®
64 and IA-32
49