Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 59

Errata
AK110. VTPR Write Access During Event Delivery May Cause an APIC-Access
VM Exit
VTPR write accesses should not cause APIC-access VM exits but instead
Problem:
should cause data to be written to the virtual-APIC page. Due to this
erratum, a VTPR write access during event delivery may cause an APIC-
access VM exit with no data being written to the virtual-APIC page.
Implication: VTPR accesses are accesses to offset 80H on the APIC-access page. VTPR
write accesses can occur during event delivery when pushing data on the
stack. Because event delivery performs multiple stack pushes, an event
delivery that includes a VTPR write access will also include at least one other
write to the APIC-access page. That other write will cause an APIC-access
VM exit. Thus, even in the presence of this erratum, any event delivery that
includes a VTPR write access will cause an APIC-access VM exit. The only
difference with respect to correct behavior will be with regard to page offset
saved in the exit qualification by the APIC-access VM exit. A VMM should be
able to emulate the event delivery correctly even with the incorrect offset.
Workaround: The VMM should emulate any event delivery that causes an APIC-access VM
exit in the same way regardless of the offset saved in the exit qualification.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK111. BIST Failure After Reset
The processor may show an erroneous BIST (built-in self test) result in bit
Problem:
[17] of EAX register when coming out of reset.
Implication: When this erratum occurs, an erroneous BIST failure will be reported in EAX
bit [17]. This failure can be ignored since it is not accurate.
Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of
the EAX register after coming out of reset.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK112. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask
Problem:
01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions.
Due to this erratum, if only a small number of MMX instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX
may be lower than expected. The degree of undercounting is dependent on
the occurrences of the erratum condition while the counter is active. Intel has
not observed this erratum with any commercially available software.
Workaround: None identified.
Intel ® Core™2 Extreme Quad-Core Processor QX6000
Intel ® Core™2 Quad Processor Q6000
Specification Update
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