Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 46

For the steppings affected, see the Summary Tables of Changes.
Status:
AK72. PEBS Buffer Overflow Status Will Not be Indicated Unless
IA32_DEBUGCTL[12] is Set
IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a
Problem:
PEBS (Precise Event-Based Sampling) overflow has occurred and a PMI
(Performance Monitor Interrupt) has been sent. Due to this erratum, this bit
will not be set unless IA32_DEBUGCTL MSR (1D9H) bit [12] (which stops all
Performance Monitor Counters upon a PMI) is also set.
Implication: Due to this erratum, IA32_PERF_GLOBAL_STATUS[62] will not indicate that a
PMI was generated due to a PEBS Overflow unless IA32_DEBUGCTL[12] is
set.
Workaround: It is possible for the software to set IA32_DEBUGCTL[12] to avoid this
erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK73. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap
Problem:
Flag, bit 8) of the EFLAGS Register is set, and a #DB (Debug Exception)
occurs due to one of the following:
• DR7 GD (General Detect, bit 13) being bit set;
• INT1 instruction;
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK74. An Asynchronous MCE During a Far Transfer May Corrupt ESP
If an asynchronous machine check occurs during an interrupt, call through
Problem:
gate, FAR RET or IRET and in the presence of certain internal
conditions, ESP may be corrupted.
Implication: If the MCE (Machine Check Exception) handler is called without a stack
switch, then a triple fault will occur due to the corrupted stack pointer,
resulting in a processor shutdown. If the MCE is called with a stack switch,
e.g., when the CPL (Current Privilege Level) was changed or when going
through an interrupt task gate, then the corrupted ESP will be saved on the
stack or in the TSS (Task State Segment), and will not be used.
Workaround: Use an interrupt task gate for the machine check handler.
For the steppings affected, see the Summary Tables of Changes.
Status:
46
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Intel Core™2 Extreme Quad-Core Processor QX6000
Sequence and Intel ® Core™2 Quad Processor Q6000
Errata
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Specification Update