Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 57

Errata
For the steppings affected, see the Summary Tables of Changes.
Status:
AK105. False Level One Data Cache Parity Machine-Check Exceptions May be
Signaled
Executing an instruction stream containing invalid instructions/data may
Problem:
generate a false Level One Data Cache parity machine-check exception.
Implication: The false Level One Data Cache parity machine-check exception is reported
as an uncorrected machine-check error. An uncorrected machine-check error
is treated as a fatal exception by the operating system and may cause a
shutdown and/or reboot.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK106. A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
The TLB (Translation Lookaside Buffer) may indicate a wrong memory type
Problem:
on a memory access to a large page (2M/4M Byte) following the recovery
from a #GP (General Protection Fault) due to a WRMSR to one of the
IA32_MTRR_PHYSMASKn MSRs with reserved bits set.
Implication: When this erratum occurs, a memory access may get an incorrect memory
type leading to unexpected system operation. As an example, an access to a
memory mapped I/O device may be incorrectly marked as cacheable, become
cached, and never make it to the I/O device. Intel has not observed this
erratum with any commercially available software.
Workaround: Software should not attempt to set reserved bits of IA32_MTRR_PHYSMASKn
MSRs.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK107. PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
When Precise Event-Based Sampling (PEBS) is configured with Performance
Problem:
Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch
Record (LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag
(bit 11) to 1 in IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon
the occurrence of a hardware PMI request. Due to this erratum, the LBR
freeze may occur too soon (i.e. before the hardware PMI request).
Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date
LBR information that does not describe the last few branches before the PEBS
sample that triggered the PMI.
Workaround: None identified.
Intel ® Core™2 Extreme Quad-Core Processor QX6000
Intel ® Core™2 Quad Processor Q6000
Specification Update
Δ Sequence and
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