Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 50

For the steppings affected, see the Summary Tables of Changes.
Status:
AK85. Non-Temporal Data Store May be Observed in Wrong Program Order
When non-temporal data is accessed by multiple read operations in one
Problem:
thread while another thread performs a cacheable write operation to the
same address, the data stored may be observed in wrong program order (i.e.
later load operations may read older data).
Implication: Software that uses non-temporal data without proper serialization before
accessing the non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel
Developer's Manual, Volume 3A, section "Buffering of Write Combining
Memory Locations" will operate correctly.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK86. Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used
Problem:
to track retired SSE instructions. Due to this erratum, the processor may
inaccurately also count certain other types of instructions resulting in higher
than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count
higher than expected.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK87. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
The ENTER instruction is used to create a procedure stack frame. Due to this
Problem:
erratum, if execution of the ENTER instruction results in a fault, the dynamic
storage area of the resultant stack frame may contain unexpected values (i.e.
residual stack data as a result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the
ENTER instruction. Please refer to "Procedure Calls For Block-Structured
Languages" in IA-32 Intel
Basic Architecture, for information on the usage of the ENTER instructions.
This erratum is not expected to occur in ring 3. Faults are usually processed
in ring 0 and stack switch occurs when transferring to ring 0. Intel has not
observed this erratum on any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
50
®
64 and IA-32 Architectures Software
®
Architecture Software Developer's Manual, Vol. 1,
®
Intel Core™2 Extreme Quad-Core Processor QX6000
Sequence and Intel ® Core™2 Quad Processor Q6000
Errata
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Δ Sequence
Specification Update