Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 52

AK91. Update of Attribute Bits on Page Directories without Immediate TLB
Shootdown May Cause Unexpected Processor Behavior
Updating a page directory entry (or page map level 4 table entry or page
Problem:
directory pointer table entry in IA-32e mode) by changing Read/Write (R/W)
or User/Supervisor (U/S) or Present (P) R/W, U/S or P bits without immediate
TLB shootdown (as described by the 4 step procedure in "Propagation of Page
Table and Page Directory Entry Changes to Multiple Processors" In volume 3A
of the Intel
conjunction with a complex sequence of internal processor micro-architectural
events, may lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially
available software.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK92. Invalid Instructions May Lead to Unexpected Behavior
Invalid instructions due to undefined opcodes or instructions exceeding the
Problem:
maximum instruction length (due to redundant prefixes placed before the
instruction) may lead, under complex circumstances, to unexpected behavior.
Implication: The processor may behave unexpectedly due to invalid instructions. Intel has
not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK93. EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
When the processor is going into shutdown due to an RSM inconsistency
Problem:
failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal
may still be asserted. This may be observed if the processor is taken out of
shutdown by NMI#.
Implication: A processor that has been taken out of shutdown may have an incorrect
EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK94. Performance Monitoring Counter MACRO_INSTS.DECODED May Not
Count Some Decoded Instructions
MACRO_INSTS.DECODED performance monitoring counter (Event 0AAH,
Problem:
Umask 01H) counts the number of macro instructions decoded, but not
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64 and IA-32 Architecture Software Developer's Manual), in
Sequence and Intel
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Intel Core™2 Extreme Quad-Core Processor QX6000
® Core™2 Quad Processor Q6000
Errata
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Specification Update