Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 22

Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK4. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
The LER MSR may be unexpectedly updated, if the resultant value of the Zero
Problem:
Flag (ZF) is zero after executing the following instructions
1) VERR (ZF=0 indicates unsuccessful segment read verification)
2) VERW (ZF=0 indicates unsuccessful segment write verification)
3) LAR (ZF=0 indicates unsuccessful access rights load)
4) LSL (ZF=0 indicates unsuccessful segment limit load)
Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR
instructions are executed after the occurrence of an exception.
Workaround: Software exception handlers that rely on the LER MSR value should read the
LER MSR before executing VERW/VERR/LSL/LAR instructions.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK5. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Performance monitoring for Event CFH normally increments on saturating
Problem:
SIMD instruction retired. Regardless of DR7 programming, if the linear
address of a retiring memory store MOVD/MOVQ/MOVNTQ instruction
executed matches the address in DR3, the CFH counter may be incorrectly
incremented.
Implication: The value observed for performance monitoring count for saturating SIMD
instructions retired may be too high. The size of the error is dependent on the
number of occurrences of the conditions described above, while the counter is
active.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK6. SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
In normal operation, SYSRET will restore the value of RFLAGS from R11 (the
Problem:
value previously saved upon execution of the SYSCALL instruction). Due to
this erratum, the RFLAGS.RF bit will be unconditionally cleared after
execution of the SYSRET instruction.
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Intel Core™2 Extreme Quad-Core Processor QX6000
Sequence and Intel ® Core™2 Quad Processor Q6000
Errata
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Δ Sequence
Specification Update