Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 54

AK97. Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
When a performance monitoring counter is configured for PEBS (Precise
Problem:
Event Based Sampling), overflow of the counter results in storage of a PEBS
record in the PEBS buffer. The information in the PEBS record represents the
state of the next instruction to be executed following the counter overflow.
Due to this erratum, if the counter overflow occurs after execution of either
MOV SS or STI, storage of the PEBS record is delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record
being delayed by one instruction following execution of MOV SS or STI. The
state information in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK98. Processor On Die Termination of BR1# and LOCK# Signals are
Incorrect
On Die Termination control of BR1# and LOCK# signals are incorrect. BR#1
Problem:
has its On Die Termination continuously enabled and LOCK# has its On Die
Termination continuously disabled.
Implication: BR1# has its On Die Termination continuously enabled meaning the VOL
(Output Low Voltage) of this signal is expected to be higher than normal
losing potential margin for nominal VCCP. LOCK# has its On Die Termination
always disabled meaning the VOL of this signal is expected to be lower than
normal and could lead to signal degradation. Even if the BR1# and Lock#
terminations are always on or always off, VOL electrical specifications are not
violated. Intel has not observed any functional failure due to this erratum.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK99. Store Ordering May be Incorrect between WC and WP Memory Types
According to Intel
Problem:
Volume 3A "Methods of Caching Available", WP (Write Protected) stores
should drain the WC (Write Combining) buffers in the same way as UC
(Uncacheable) memory type stores do. Due to this erratum, WP stores may
not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
54
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64 and IA-32 Architectures Software Developer's Manual,
Intel
Sequence and Intel
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Core™2 Extreme Quad-Core Processor QX6000
® Core™2 Quad Processor Q6000
Errata
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