Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 38

execution flow that results in a Code Segment Limit or Canonical Fault, the
#GP fault may be serviced before a higher priority Interrupt or Exception
(e.g. NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check
(#MC), etc.)
Implication: Operating systems may observe a #GP fault being serviced before higher
priority Interrupts and Exceptions. Intel has not observed this erratum on any
commercially available software.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK49. VM Bit is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
Following a task switch to any fault handler that was initiated while the
Problem:
processor was in VM86 mode, if there is an additional fault while servicing the
original task switch then the VM bit will be incorrectly cleared in EFLAGS, data
segments will not be pushed and the processor will not return to the correct
mode upon completion of the second fault handler via IRET.
Implication: When the OS recovers from the second fault handler, the processor will no
longer be in VM86 mode. Normally, operating systems should prevent
interrupt task switches from faulting, thus the scenario should not occur
under normal circumstances.
Workaround: None Identified
For the steppings affected, see the Summary Tables of Changes.
Status:
AK50. IA32_FMASK is Reset during an INIT
IA32_FMASK MSR (0xC0000084) is reset during INIT.
Problem:
Implication: Implication: If an INIT takes place after IA32_FMASK is programmed, the
processor will overwrite the value back to the default value.
Workaround: Operating system software should initialize IA32_FMASK after INIT.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK51. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
A MOV SS/POP SS instruction should inhibit all interrupts including debug
Problem:
breakpoints until after execution of the following instruction. This is intended
to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP,
[r/e]BP instructions without having an invalid stack during interrupt handling.
However, an enabled debug breakpoint or single step trap may be taken after
MOV SS/POP SS if this instruction is followed by an instruction that signals a
floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This
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Intel Core™2 Extreme Quad-Core Processor QX6000
Sequence and Intel ® Core™2 Quad Processor Q6000
Errata
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Δ Sequence
Specification Update