Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 13

Summary Tables of Changes
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Intel ® Core™2 Extreme Quad-Core Processor QX6000
Intel ® Core™2 Quad Processor Q6000
Specification Update
B3 G0 Plan
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Δ Sequence
ERRATA
Values for LBR/BTS/BTM will be Incorrect after an Exit from
SMM
Shutdown Condition May Disable Non-Bootstrap Processors
SYSCALL Immediately after Changing EFLAGS.TF May Not
Behave According to the New EFLAGS.TF
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions
VM Bit is Cleared on Second Fault Handled by Task Switch
from Virtual-8086 (VM86)
IA32_FMASK is Reset during an INIT
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
Last Branch Records (LBR) Updates May be Incorrect after a
Task Switch
IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
INIT Does Not Clear Global Entries in the TLB
Using Memory Type Aliasing with Memory Types WB/WT May
Lead to Unpredictable Behavior
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
BTS Message May Be Lost When the STPCLK# Signal is
Active
CMPSB, LODSB, or SCASB in 64-bit Mode with Count
Greater or Equal to 2 48 May Terminate Early
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
may use an Incorrect Data Size or Lead to Memory-Ordering
Violations
MOV To/From Debug Registers Causes Debug Exception
Unaligned Accesses to Paging Structures May Cause the
Processor to Hang
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM
Exits after a Translation Change
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
Returning to Real Mode from SMM with EFLAGS.VM Set May
Result in Unpredictable System Behavior
A Thermal Interrupt is Not Generated when the Current
Temperature is Invalid
VMLAUNCH/VMRESUME May Not Fail when VMCS is
Programmed to Cause VM Exit to Return to a Different
Mode
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
Δ Sequence and 13