Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 24

Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK10. Debug Register May Contain Incorrect Information on a MOVSS or
POPSS Instruction Followed by SYSRET
In IA-32e mode, if a MOVSS or POPSS instruction with a debug breakpoint is
Problem:
followed by the SYSRET instruction; incorrect information may exist in the
Debug Status Register (DR6).
Implication: When debugging or when developing debuggers, this behavior should be
noted. This erratum will not occur under normal usage of the MOVSS or
POPSS instructions (i.e., following them with a MOV ESP instruction).
Workaround: Do not attempt to put a breakpoint on MOVSS and POPSS instructions that
are followed by a SYSRET.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK11. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
With respect to the retirement of instructions, stores to the uncacheable
Problem:
memory-based APIC register space are handled in a non-synchronized way.
For example if an instruction that masks the interrupt flag, e.g. CLI, is
executed soon after an uncacheable write to the Task Priority Register (TPR)
that lowers the APIC priority, the interrupt masking operation may take effect
before the actual priority has been lowered. This may cause interrupts whose
priority is lower than the initial TPR, but higher than the final TPR, to not be
serviced until the interrupt enabled flag is finally set, i.e. by STI instruction.
Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may
delay their service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read
after the APIC register write. This will force the store to the APIC register
before any subsequent instructions are executed. No commercial operating
system is known to be impacted by this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK12. Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
Software can enable DTS thermal interrupts by programming the thermal
Problem:
threshold and setting the respective thermal interrupt enable bit. When
programming DTS value, the previous DTS threshold may be crossed. This
will generate an unexpected thermal interrupt.
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Intel Core™2 Extreme Quad-Core Processor QX6000
Sequence and Intel ® Core™2 Quad Processor Q6000
Errata
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Specification Update