Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 53

Errata
necessarily retired. The event is undercounted when the decoded
instructions are a complete loop iteration that is decoded in one cycle and the
loop is streamed by the LSD (Loop Stream Detector), as described in the
Optimizing the Front End section of the Intel
Optimization Reference Manual.
Implication: The count value returned by the performance monitoring counter
MACRO_INST.DECODED may be lower than expected. The degree of
undercounting is dependent on the occurrence of loop iterations that are
decoded in one cycle and whether the loop is streamed by the LSD while the
counter is active.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK95. The Stack Size May be Incorrect as a Result of VIP/VIF Check on
SYSEXIT and SYSRET
The stack size may be incorrect under the following scenario:
Problem:
The stack size was changed due to a SYSEXIT or SYSRET
•
PVI (Protected Mode Virtual Interrupts) mode was enabled (CR4.PVI == 1)
•
Both the VIF (Virtual Interrupt Flag) and VIP (Virtual Interrupt Pending) flags of
•
the EFLAGS register are set
Implication: If this erratum occurs the stack size may be incorrect, consequently this may
result in unpredictable system behavior. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK96. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select
Problem:
0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops
executed. The count for PMULUDQ micro-ops may be lower than expected.
No other instruction is affected.
Implication: The count value returned by the performance monitoring event
SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree of
undercount depends on actual occurrences of PMULUDQ instructions, while
the counter is active.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
Intel ® Core™2 Extreme Quad-Core Processor QX6000
Intel ® Core™2 Quad Processor Q6000
Specification Update
Δ Sequence and
Δ Sequence
®
64 and IA-32 Architectures
53