Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 11

Summary Tables of Changes
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Intel ® Core™2 Extreme Quad-Core Processor QX6000
Intel ® Core™2 Quad Processor Q6000
Specification Update
B3 G0 Plan
X X No Fix
X Fixed
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X Fixed
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Δ Sequence
ERRATA
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance
Monitoring Count for Saturating SIMD Instructions Retired
(Event CFH)
SYSRET May Incorrectly Clear RF (Resume Flag) in the
RFLAGS Register
General Protection Fault (#GP) for Instructions Greater than
15 Bytes May be Preempted
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
The Processor May Report a #TS Instead of a #GP Fault
Debug Register May Contain Incorrect Information on a
MOVSS or POPSS Instruction Followed by SYSRET
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
Programming the Digital Thermal Sensor (DTS) Threshold
May Cause Unexpected Thermal Interrupts
Count Value for Performance-Monitoring Counter
PMH_PAGE_WALK May be Incorrect
LER MSRs May be Incorrectly Updated
Performance Monitoring Events for Retired Instructions
(C0H) May Not Be Accurate
Performance Monitoring Event For Number Of Reference
Cycles When The Processor Is Not Halted (3CH) Does Not
Count According To The Specification
Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
Code Segment Limit Violation May Occur on 4 Gigabyte
Limit Check
FP Inexact-Result Exception Flag May Not Be Set
Global Pages in the Data Translation Look-Aside Buffer
(DTLB) May Not Be Flushed by RSM instruction before
Restoring the Architectural State from SMRAM
Sequential Code Fetch to Non-canonical Address May have
Non-deterministic Results
VMCALL to Activate Dual-monitor Treatment of SMIs and
SMM Ignores Reserved Bit settings in VM exit Control Field
The PECI Controller Resets to the Idle State
Some Bus Performance Monitoring Events May Not Count
Local Events under Certain Conditions
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