Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 12

NO B3
AK26 X
AK27 X
AK28 X
AK29 X
AK30 X
AK31 X
AK32 X
AK33 X
AK34 X
AK35 X
AK36 X
AK37 X
AK38 X
AK39 X
AK40 X
AK41 X
AK42 X
AK43 X
AK44 X
12
G0 Plan ERRATA
Premature Execution of a Load Operation Prior to Exception
X No Fix
Handler Invocation
General Protection (#GP) Fault May Not Be Signaled on
X No Fix
Data Segment Limit Violation above 4-G Limit
X No Fix EIP May be Incorrect after Shutdown in IA-32e Mode
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE
X No Fix
[34] When Execute Disable Bit is Not Supported
(E)CX May Get Incorrectly Updated When Performing Fast
Fixed String REP MOVS or Fast String REP STOS With Large Data
Structures
Performance Monitoring Events for Retired Loads (CBH) and
Fixed
Instructions Retired (C0H) May Not Be Accurate
Upper 32 bits of 'From' Address Reported through BTMs or
X No Fix
BTSs May be Incorrect
Unsynchronized Cross-Modifying Code Operations Can
Fixed
Cause Unexpected Instruction Execution Results
MSRs Actual Frequency Clock Count (IA32_APERF) or
Maximum Frequency Clock Count (IA32_MPERF) May
X No Fix
Contain Incorrect Data after a Machine Check Exception
(MCE)
Incorrect Address Computed For Last Byte of
X No Fix
FXSAVE/FXRSTOR Image Leads to Partial Memory Update
Split Locked Stores May not Trigger the Monitoring
X No Fix
Hardware
REP CMPS/SCAS Operations May Terminate Early in 64-bit
Fixed
Mode when RCX >= 0X100000000
FXSAVE/FXRSTOR Instructions which Store to the End of the
Segment and Cause a Wrap to a Misaligned Base Address
Fixed
(Alignment <= 0x10h) May Cause FPU Instruction or
Operand Pointer Corruption
Cache Data Access Request from One Core Hitting a
Fixed Modified Line in the L1 Data Cache of the Other Core May
Cause Unpredictable System Behavior
PREFETCHh Instruction Execution under Some Conditions
Fixed
May Lead to Processor Livelock
PREFETCHh Instructions May Not be Executed when
Fixed
Alignment Check (AC) is Enabled
Upper 32 Bits of the FPU Data (Operand) Pointer in the
Fixed FXSAVE Memory Image May Be Unexpectedly All 1's after
FXSAVE
Concurrent Multi-processor Writes to Non-dirty Page May
Fixed
Result in Unpredictable Behavior
Performance Monitor IDLE_DURING_DIV (18h) Count May
Fixed
Not be Accurate
Intel
Sequence and Intel
Summary Tables of Changes
®
Core™2 Extreme Quad-Core Processor QX6000
® Core™2 Quad Processor Q6000
Δ
Δ Sequence
Specification Update