Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification page 40

AK54. INIT Does Not Clear Global Entries in the TLB
INIT may not flush a TLB entry when:
Problem:
• The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
• G bit for the page table entry is set
• TLB entry is present in TLB when INIT occurs
• Implication: Software may encounter unexpected page fault or incorrect address
translation due to a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or
PE) registers before writing to memory early in BIOS code to clear all the
global entries from TLB.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Memory type aliasing occurs when a single physical page is mapped to two or
Problem:
more different linear addresses, each with different memory type. Memory
type aliasing with the memory types WB and WT may cause the processor to
perform incorrect operations leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe
unpredictable behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AK56. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
(P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Updating a page table entry by changing R/W, U/S or P bits without TLB
Problem:
shootdown (as defined by the 4 step procedure in "Propagation of Page Table
and Page Directory Entry Changes to Multiple Processors" in volume 3A of the
IA-32 Intel
complex sequence of internal processor micro-architectural events, may lead
to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially available
system.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
40
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Architecture Software Developer's Manual), in conjunction with a
Sequence and Intel
®
Intel Core™2 Extreme Quad-Core Processor QX6000
® Core™2 Quad Processor Q6000
Errata
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Δ Sequence
Specification Update