Xilinx SP605 User Manual page 27

Table 1-10: GTP SMA Clock Connections
SP605 Hardware User Guide
UG526 (v1.1.1) February 1, 2010
U1 FPGA Pin Schematic Net Name
C9 SMA_RX_N
D9 SMA_RX_P
A8 SMA_TX_N
B8 SMA_TX_P
D11 SMA_REFCLK_N
C11 SMA_REFCLK_P
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Detailed Description
SMA Pin
J35.1
J34.1
J33.1
J32.1
J36.1
J37.1
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