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S3F80P5_UM_ REV1.00
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The
SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific
interrupt level has more than one vector address, the vector priorities are established in hardware. A vector
address can be assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are seven
possible interrupt levels: IRQ0−IRQ7(IRQ5 is reserved for S3F80P5), also called level 0 − level 7 (level 5 is
reserved for S3F80P5). Each interrupt level directly corresponds to an interrupt request number (IRQn). The total
number of interrupt levels used in the interrupt structure varies from device to device. The S3F80P5 interrupt
structure recognizes seven interrupt levels.
The interrupt level numbers 0 through 7 (5 is reserved for S3F80P5) do not necessarily indicate the relative
priority of the levels. They are simply identifiers for the interrupt levels that are recognized by the CPU. The
relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt
group and subgroup logic controlled by IPR register settings lets you define more complex priority relationships
between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The
maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors used
for S3C8/S3F8-series devices is always much smaller.) If an interrupt level has more than one vector address,
the vector priorities are set in hardware. The S3F80P5 uses fourteen vectors. One vector addresses are shared
by four interrupt sources.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for
example. Each vector can have several interrupt sources. In the S3F80P5 interrupt structure, there are 17
possible interrupt sources.
When a service routine starts, the respective pending bit is either cleared automatically by hardware or is must be
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method is used to clear its respective pending bit.
5-1
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