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S3F80P5_UM_ REV1.00
CACON
— Counter A Control Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3
.2
.1
.0
.7
.6
0
0
R/W
R/W
Register addressing mode only
Counter A Input Clock Selection Bits
f
0
0
OSC
f
/2
0
1
OSC
f
/4
1
0
OSC
f
/8
1
1
OSC
Counter A Interrupt Timing Selection Bits
0
0
Elapsed time for Low data value
0
1
Elapsed time for High data value
1
0
Elapsed time for combined Low and High data values
1
1
Not used for S3F80P5.
Counter A Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Counter A Start Bit
0
Stop counter A
1
Start counter A
Counter A Mode Selection Bit
0
One-shot mode
1
Repeating mode
Counter A Output Flip-Flop Control Bit
0
Flip-Flop Low level (T-FF = Low)
1
Flip-flop High level (T-FF = High)
.5
.4
0
0
R/W
R/W
R/W
CONTROL REGISTERS
F3H
.3
.2
.1
0
0
0
R/W
R/W
Set1 Bank0
.0
0
R/W
4-7
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