Samsung S3F80P5X User Manual page 79

S3F80P5_UM_ REV1.00
LVDCON
— LVD Control Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7− .1
.0
NOTE: When LVD detects LVD_FLAG level, LVDCON.0 flag bit is set automatically. When VDD is upper LVD_FLAG level,
LVDCON.0 flag bit is cleared automatically.
.7 .6
− −
− −
Register addressing mode only
Not used for S3F80P5.
LVD Flag Indicator Bit
V LVD_FLAG Level
0
DD ≥
< LVD_FLAG Level
1
V
DD
.5 .4 .3
− − −
− − −
CONTROL REGISTERS
E0H Set1 Bank1
.2 .1 .0
− −
0
− −
R/W
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