System Clock Control Register (Clkcon) - Samsung KS86C6004 Manual

CLOCK CIRCUIT

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:
— Oscillator IRQ wake-up function enable/disable (CLKCON.7)
— Oscillator frequency divide-by value: non-divided, 2, 8 or 16 (CLKCON.4 and CLKCON.3)
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
f /16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU
OSC
clock speed to f , f
OSC OSC
MSB
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main system
oscillator wake-up function
1 = Disable IRQ for main system
oscillator wake-up function
Not used for KS86C6004/C6008/P6008
7-2
KS86C6004/C6008/P6008 MICROCONTROLLERS (Preliminary Spec)
/2 or f /8.
OSC
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
.7 .6 .5
Figure 7-2. System Clock Control Register (CLKCON)
D4H, R/W
.4 .3 .2
Not used for KS86C6004/C6008/P6008
Divide-by selection bits for
CPU clock frequency:
00 = fOSC/16
01 = fOSC/8
10 = fOSC/2
11 = fOSC (non-divided)
.1 .0 LSB