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INSTRUCTION SET
DECW
— Decrement Word
DECW
dst
dst ← dst – 1
Operation:
The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
opc
Examples:
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW RR0
DECW @R2
In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word
and decrements the value of R1 by one, leaving the value 33H.
NOTE:
A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW
instruction. To avoid this problem, we recommend that you use DECW as shown in the following
example:
LOOP: DECW RR0
LD R2,R1
OR R2,R0
JR NZ,LOOP
6-36
dst
→ R0 = 12H, R1 = 33H
→ Register 30H = 0FH, register 31H = 20H
Bytes
Cycles
Opcode
2
8
8
S3F80P5_UM_ REV1.00
Addr Mode
(Hex)
dst
80
RR
81
IR
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