Samsung S3F80P5X User Manual page 75

S3F80P5_UM_ REV1.00
IMR
— Interrupt Mask Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7
.6
.5
.4
.3
.2
.1
.0
.7 .6
x x
R/W R/W
Register addressing mode only
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
0 Disable (mask)
1 Enable (un-mask)
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0 Disable (mask)
1 Enable (un-mask)
Not used for S3F80P5
Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.0
0 Disable (mask)
1 Enable (un-mask)
Interrupt Level 3 (IRQ3) Enable Bit; Timer 2 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt
0 Disable (mask)
1 Enable (un-mask)
Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
.5 .4
x x
R/W R/W R/W
CONTROL REGISTERS
DDH Set1 Bank0
.3 .2 .1
x x x
R/W R/W
.0
x
R/W
4-13