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RESET
Watchdog Timer
P0&P2.0
(INT0-INT5)
(EI)external interrupt enable
RESET Contorl Bit '1'
STOP
RESET Contorl Bit '1'
STOP
1. The rising edge detection of LVD circuit while rising of VDD passes the level of V
2.
When POR circuit detects VDD below V
3.
Basic Timer over-flow for watchdog timer. See the chapter 10. Basic Timer and Timer 0 for more
understanding.
4. When RESET Control Bit (smart option @ 03FH) is set to '0' and chip is in stop mode, external interrupt input
by P0 and P2.0 generates the reset signal.
5. When RESET Control Bit (smart option @ 03FH) are set to '0' and chip is in stop mode or abnormal state, the
falling edge input of P0 generates the reset signal regardless of external interrupt enable/disable.
8-2
STOP
LVD
IPOR
P0
Figure 8-1. RESET Sources of the S3F80P5
, reset is generated by internal power-on reset.
POR
1
2
3
4
5
*RESET Control Bit : smart option bit[0]@03FH
LVD
S3F80P5_UM_ REV1.00
RESET
.
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