Samsung S3F80P5X User Manual page 298

S3F80P5_UM_ REV1.00
NOTE: The voltage gaps (LVD_GAPn (n=1~4)) between LVD and LVD FLAGn(n=1~4) have ± 80mV distribution. LVD and
LVD FLAGn(n=1~4) are not overlapped. The variation of LVD FLAGn(n=1~4) and LVD always is shifted in same
direction. That is, if one chip has positive tolerance (e.g. +50mV) in LVD FLAG, LVD has positive tolerance.
Symbol
LVD_GAP1
LVD_GAP2
LVD_GAP3
LVD_GAP4
Symbol
GAP Between LVD_Flag1 and LVD_Flag2
GAP Between LVD_Flag2 and LVD_Flag3
GAP Between LVD_Flag3 and LVD_Flag4
= -25 °C to + 85 °C)
(T
A
Parameter
Power on reset (POR)
Voltage
= -25 °C to + 85 °C)
(T
A
Parameter
Data Retention Supply
Voltage
Data Retention Supply
Current
Data Retention Supply Current means that the minimum supplied current for data retention.
NOTE:
battery voltage is not sufficient (i,e, the supply current is <1uA), the data retention could be not be guaranteed.
Table 16-4. Power On Reset Circuit
Symbol
V
POR
Table 16-5. Data Retention Supply Voltage in Stop Mode
Symbol
V
DDDR
I
DDDR
Min Typ
150 230
250 330
800 880
1000 1080
Min Typ
50 100
500 550
150 200
Conditions
−
Conditions
−
V = 1.0 V
DDDR
Stop Mode
ELECTRICAL DATA
Max
310
410
960
1160
Max
150
600
250
Min Typ Max
0.8 1.1 1.4
Min Typ Max
−
0.8 3.6
− −
Unit
mV
mV
mV
mV
Unit
mV
mV
mV
Unit
V
Unit
V
μA
1
When the
16-5