Samsung S3F80P5X User Manual page 82

S3f80p5 microcontrollers
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CONTROL REGISTERS
P0CONL
— Port 0 Control Register (Low Byte)
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7 and .6
.5 and .4
.3 and .2
.1 and .0
NOTES:
1.
The INT3−INT0 external interrupts at P0.3−P0.0 are interrupt level IRQ6. Each interrupt has a separate vector address.
2.
You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
(P0PUR.3 − P0PUR.0)
4-20
.7
.6
0
0
R/W
R/W
Register addressing mode only
P0.3/INT3 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
P0.2/INT2 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
P0.1/INT1 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
P0.0/INT0 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
.5
.4
0
0
R/W
R/W
R/W
S3F80P5_UM_ REV1.00
E9H
Set1 Bank0
.3
.2
.1
0
0
0
R/W
R/W
.0
0
R/W

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