System Clock Control Register (Clkcon) - Samsung S3C8275X User Manual

CLOCK CIRCUIT

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in the set 1, at address D4H. It is read/write addressable
and has the following functions:
•
Oscillator IRQ wake up function enable/disable
•
Oscillator frequency divide-by value
CLKCON register settings control whether or not an external interrupt can be used to trigger a stop mode release
(This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7.
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed to f
Oscillator IRQ wake-up function bit:
0 = Enable IRQ for main wake up in
power down mode
1 = Disable IRQ for main wake up in
power down mode
Not used for S3C8275X/C8278X/C8274X
(must keep always 0)
7-4
System Clock Control Register (CLKCON)
MSB .7 .6 .5
Figure 7-7. System Clock Control Register (CLKCON)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
/8, f /2, or f
xx xx xx
D4H, Set 1, R/W
.4 .3 .2 .1
Not used for S3C8275X/C8278X/C8274X
(must keep always 0)
Divide-by selection bits for
CPU clock frequency:
00 = fxx/16
01 = fxx/8
10 = fxx/2
11 = fxx/1 (non-divided)
/1.
.0 LSB