Interrupt Pending Function Types; Overview; Pending Bits Cleared Automatically By Hardware; Pending Bits Cleared By The Service Routine - Samsung S3F80P5X User Manual

INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00

INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt
service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is
waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service
routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or
written by application software.
In the S3F80P5 interrupt structure, the timer 0 overflow interrupt (IRQ0), the timer 1 overflow interrupt (IRQ1) and
the counter A interrupt (IRQ2) belong to this category of interrupts whose pending condition is cleared
automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit must be cleared by program software. The service routine must clear the
appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written
to the corresponding pending bit location in the source's mode or control register.
In the S3F80P5 interrupt structure, pending conditions for all interrupt sources except the timer 0 overflow
interrupt, the timer 1 overflow interrupt and the counter A borrow interrupt, must be cleared by the interrupt
service routine.
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