I2C\Smbus Architecture Block; I2C\Smbus Device Addresse; Figure 20. S5500Wb I2C\Smbus Block Diagram; Table 16. I2C/Smbus Device Address Assignment - Intel S5500WB12V Specification

Platform Management Features
5.6

I2C\SMBUS Architecture Block

5.6.1 I2C\SMBUS Device Addresses
Table 21 lists the I2C\SMBus addresses of various devices by bus.
Main Power Sub
Bus Rail Bus
Host 3V3SB NA
Host
Sensor 3V3SB NA
IPMI 3V3SB NA
IPMI
IPMI
44
S5500WB I2C\SMBUS Block Diagram
Figure 20.

Table 16. I2C/SMBus Device Address Assignment

Power Device
Rail
NA IBMC I2C\SMBus 3
ICH10R SMBus
CK509B
DB403
3V3 XDP
DB803
CPU0 DIMM 1A
CPU0 DIMM 2A
CPU0 DIMM 1B
CPU0 DIMM 1C
CPU0 DIMM 1D
CPU0 DIMM 2D
CPU0 DIMM 1E
CPU0 DIMM 1F
NA IBMC I2C\SMBus 1
Temp Sensor
FP Temp Sensor
FP FRU
Baseboard FRU
CPU IOH
NA IBMC I2C\SMBus 0
5VSB IPMI Connector
5V HSBP A
Intel order number E53971-008
Intel® Server Board S5500WB TPS
I2C\SMBus
Address
No Connect
0x88
0xD2
0xDC
0xDC
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
0xAC
0xAE
0x9E
0x9A
0xAE
0xA8
0xE0
0xC0
Note
Revision 1.9