Figure 13. Block Diagram Of Platform Managment Architecture - Intel SE7525GP2 Technical Manual

Platform Management
HECETA 7
P1_VID[5:0]
VID_CPU0[5:0]
P1_Prochot_N
P2_VID[5:0] P2_Prochot_N
VID_CPU1[5:0]
+12V1
Not Used P1_Thermtrip_N
P12V_CPU_SCALED +12V2
P12V_SCALED
+12V3
P_VT
FSB_Vtt
Chipset_Core
P1V
ICH_Core
P2_Thermtrip_N
Not Used
CPU1_Vccp
P_VCCP0
CPU2_Vccp
P_VCCP1
3.3V
P3V
P5V
+5V
PWM1
SCSI_Core
P1V8_SCSI DDR Core
Mem_Core
DDR
Mem_Vtt
Gb LAN Core
GBIT _Core
Tach
-12V
N12V_SCALED
+3.3 S/B Vcc
P3V3_ STBY
Tach
SCSI_term1
SCSIA_TERMPWR
SCSI_term2
SCSIB_TERMPWR
CPU1 Thermal Diode RTD
Tach
CPU2Thermal Diode RTD
Tach
PWM2
CPU 1 IERR GPI
GPI
CPU 2 IERR
8742X SIO
FANIN6
FANIN5
FANIN1
FANIN3
CHASSIS INTRUSION
Chassis
Security
SECURE_MODE_KB
LED
96
Intel® Server Boards SE7320SP2 and SE7525GP2
CPU1_PROCHOT_N
GTL to
translation
Logic
CPU2_PROCHOT_N
GTL to
translation
Logic
GTL to
translation
Logic
AND
GTL to
translation
Logic
FET
Zone
AM
CPU
FAN
CPU
FAN
Fa
n
FET
Zone
Fan
AM
FA
FA
Mem
FA
PWR_LED

Figure 13. Block Diagram of Platform Managment Architecture

FMC_CPU1_SKTOCC_N
CPU1
FMC_CPU2_SKTOCC_N
CPU2
6300ESB
SPK
SPEAKER
Thermtrip
Front Panel
Connector
FP_ID_BTN_N
FP_ID_LED_N
FP_SYS_FLT_LED_A
FP_SYS_FLT_LED_C
FP_RST_BTN
FP_PWR_BTN
FP_NMI_BTN
FRB3_TMR_HALT_N
PS_PWR_GD
SECURE_MODE_KB
CPU_CFG_ERR_N
Revision 4.0
CPU1 VRD OUTEN &
System PWRGD Logic
CPU2 VRD OUTEN Logic
SUS_STAT_
GPIO48
GPIO40
RTCRST_N
mBM
GP
LED
CPU1_SEL
GP
LEDC
CPU2_SEL
GP
LED
LEDC
ICH_RST_BTN
RSTout
RSTi
ICH_PWR_BTN
PWBout
PWBin
SYS_NMI
GP NM
SYS_SMI
SM
GP
PWRGD
GP
GP
GP
GND