Table 57. Diagnostic Led Post Code Decoder - Intel S5500WB12V Specification

Intel® Server Board S5500WB TPS
Diagnostic LED Decoder
Checkpoint Upper Nibble
MSB
8h 4h
LED #7 #6
Host Processor
0x10h 0 0
0x11h 0 0
0x12h 0 0
0x13h 0 0
0x14h 0 0
0x15h 0 0
Chipset
0x21h 0 0
Memory
0x22h 0 0
0x23h 0 0
0x24h 0 0
0x25h 0 0
0x26h 0 0
0x27h 0 0
0x28h 0 0
0xE4h 1 1
0xE6h 1 1
0xE8h 1 1
0xE9h 1 1
0xEAh 1 1
0xEBh 1 1
0xECh 1 1
0xEDh 1 1
0xEBh 1 1
Revision 1.9

Table 57. Diagnostic LED POST Code Decoder

1 = On, 0=Off
Lower Nibble
2h 1h 8h 4h 2h
#5 #4 #3 #2 #1
0 1 0 0 0
0 1 0 0 0
0 1 0 0 1
0 1 0 0 1
0 1 0 1 0
0 1 0 1 0
1 0 0 0 0
1 0 0 0 1
1 0 0 0 1
1 0 0 1 0
1 0 0 1 0
1 0 0 1 1
1 0 0 1 1
1 0 1 0 0
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 0
1 0 1 0 1
1 0 1 0 1
1 0 1 1 0
1 0 1 1 0
1 0 1 0 1
Intel order number E53971-008
LSB
1h
#0
0 Power-on initialization of the host processor (bootstrap processor)
1 Host processor cache initialization (including AP)
0 Starting application processor initialization
1 SMM initialization
Selection of Processor with least features to be used as Boot Strap
0
Processor
1 Switch an AP processor to become the new Boot Strap Processor
1 Initializing a chipset component
0 Reading configuration data from memory (SPD on FBDIMM)
1 Detecting presence of memory
0 Programming timing parameters in the memory controller
1 Configuring memory parameters in the memory controller
0 Optimizing memory controller settings
1 Initializing memory, such as ECC init
0 Testing memory
BIOS cannot communicate with DIMM (serial channel hardware
0
failure)
0 DIMM(s) failed Memory iBIST or Memory Link Training failure
0 No memory available (system halted)
1 Unsupported or invalid DIMM configuration (system halted)
0 DIMM training sequence failed (system halted)
1 Memory test failed (system halted)
0 Unsupported or invalid DIMM configuration (system halted)
1 Unsupported or invalid DIMM configuration (system halted)
1 DIMM with corrupted SPD data detected (system halted)
Appendix A: POST Code LED Decoder
Description
91