Mc_Channel_0_Dimm_Init_Cmd; Mc_Channel_1_Dimm_Init_Cmd; Mc_Channel_2_Dimm_Init_Cmd - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

2.10.2

MC_CHANNEL_0_DIMM_INIT_CMD

MC_CHANNEL_1_DIMM_INIT_CMD

MC_CHANNEL_2_DIMM_INIT_CMD

Integrated Memory Controller DIMM initialization command register. This register is
used to sequence the channel through the physical layer training required for DDR.
Device:
Function: 0
Offset:
Access as a Dword
Bit
17
16
15
14
13
12
11
10
9
8
7:5
4:2
1
0
60
4, 5, 6
54h
Reset
Type
Value
ASSERT_CKE.
When set, all CKE will be asserted. Write a 0 to this bit to stop the init block
from driving CKE. This bit has no effect once MC_CONTROL.INIT_DONE is set.
WO 0
This bit must be used during INITIALIZATION only and be cleared out before
MC_CONTROL.INIT_DONE is set. This bit must not be asserted during
initialization for S3 resume.
DO_RCOMP.
RW 0
When set, an RCOMP will be issued to the rank specified in the RANK field.
DO_ZQCL.
RW 0
When set, a ZQCL will be issued to the rank specified in the RANK field.
WRDQDQS_MASK.
RW 0
When set, the Write DQ-DQS training will be skipped.
WRLEVEL_MASK.
RW 0
When set, the Write Levelization step will be skipped.
RDDQDQS_MASK.
RW 0
When set, the Read DQ-DQS step will be skipped.
RCVEN_MASK.
RW 0
When set, the RCVEN step will be skipped.
RESET_FIFOS.
WO 0
When set, the TX and RX FIFO pointers will be reset at the next BCLK edge. The
Bubble Generators will also be reset.
IGNORE_RX.
RW 0
When set, the read return datapath will ignore all data coming from the RX
FIFOS. This is done by gating the early valid bit.
STOP_ON_FAIL.
RW 0
When set along with the AUTORESETDIS not being set, the phyinit FSM will stop
if a step has not completed after timing out.
RANK.
RW 0
The rank currently being tested. The PhyInit FSM must be sequenced for every
rank present in the channel. The rank value is set to the rank being trained.
NXT_PHYINIT_STATE.
Set to sequence the physical layer state machine.
000 = IDLE
RW 0
001 = RD DQ-DQS
010 = RcvEn Bitlock
011 = Write Level
100 = WR DQ-DQS.
AUTODIS.
Disables the automatic training where each step is automatically incremented.
RW 0
When set, the physical layer state machine must be sequenced with software.
The training FSM must be sequenced using the NXT_PHYINIT_STATE field.
TRAIN.
WO 0
Cycle through the training sequence for the rank specified in the RANK field.
Register Description
Description
Datasheet