Mc_Channel_0_Cke_Timing Mc_Channel_1_Cke_Timing; Mc_Channel_2_Cke_Timing; Mc_Channel_0_Zq_Timing; Mc_Channel_2_Zq_Timing - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

Register Description
2.10.14 MC_CHANNEL_0_CKE_TIMING
MC_CHANNEL_1_CKE_TIMING

MC_CHANNEL_2_CKE_TIMING

This register contains parameters that specify the CKE timings. All units are in DCLK.
Device:
Function: 0
Offset:
Access as a Dword
Bit
31:24
23:21
20:11
10:3
2:0
2.10.15

MC_CHANNEL_0_ZQ_TIMING

MC_CHANNEL_1_ZQ_TIMING

MC_CHANNEL_2_ZQ_TIMING

This register contains parameters that specify ZQ timing. All units are DCLK unless
otherwise specified. The register encodings are specified where applicable.
Device:
Function: 0
Offset:
Access as a Dword
Bit
30
29
28:8
7:5
4:0
Datasheet
4, 5, 6
90h
Reset
Type
Value
tRANKIDLE.
Rank will go into powerdown after it has been idle for the specified number of
dclks. tRANKIDLE covers max(txxxPDEN). Minimum value is tWRAPDEN. If CKE
RW 0
is being shared between ranks then both ranks must be idle for this amount of
time. A Power Down Entry command will be requested for a rank after this
number of DCLKs if no request to the rank is in the MC.
tXP.
Minimum delay from exit power down with DLL and any valid command. Exit
RW 0
Precharge Power Down with DLL frozen to commands not requiring a locked
DLL. Slow exit precharge powerdown is not supported.
tXSDLL.
RW 0
Minimum delay between the exit of self refresh and commands that require a
locked DLL.
tXS.
RW 0
Minimum delay between the exit of self refresh and commands not requiring a
DLL.
tCKE.
RW 0
CKE minimum pulse width.
4, 5, 6
94h
Reset
Type
Value
Parallel_ZQ.
RW 1
Enable ZQ calibration to different ranks in parallel.
tZQenable.
RW 1
Enable the issuing of periodic ZQCS calibration commands.
ZQ_Interval.
RW 16410
Nominal interval between periodic ZQ calibration in increments of tREFI.
tZQCS.
This field specifies ZQCS cycles in increments of 16. This is the minimum delay
RW 4
between ZQCS and any other command. This register should be programmed to
at least 64/16=4='100' to conform to the DDR3 specification.
tZQInit.
This field specifies ZQInit cycles in increments of 32. This is the minimum delay
RW 0
between ZQCL and any other command. This register should be programmed to
at least 512/32=16='10000' to conform to the DDR3 specification.
Description
Description
71