Mc_Scrubaddr_Hi - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

2.8.11

MC_SCRUBADDR_HI

This register pair contains part of the address of the last patrol scrub request issued.
When running memtest, the failing address is logged in this register on memtest
errors. Software can write the next address into this register. Scrubbing must be
disabled to reliably read and write this register.
Device:
Function: 0
Offset:
Access as a Dword
Bit
9:8
7:6
5:4
3:0
56
3
7Ch
Reset
Type
Value
CHNL.
This field can be written to specify the next scrub address with STARTSCRUB in
RW 0
the MC_SCRUB_CONTROL register. This register is not updated with channel
address of the last scrub address issued.
DIMM.
This field contains the DIMM of the last scrub issued. Can be written to specify
the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
RW 0
For writes, to the register this field always contains the Rank ID. For reads, the
following translation must be done:
If 3 DIMMs are on the channel, then the rank is RANK[0] while the dimm is the
concatenation of DIMM[0] and RANK[1].
RANK.
This field contains the rank of the last scrub issued. Can be written to specify
the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL
RW 0
register.. For writes, to the register this field always contains the rank id. For
reads, the following translation must be done:
If 3 dimms are on the channel then the rank is RANK[0] while the dimm is the
concatenation of DIMM[0] and RANK[1].
BANK.
This field contains the bank of the last scrub issued. Can be written to specify
RW 0
the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL
register..
Register Description
Description
Datasheet