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2.10.12
MC_CHANNEL_0_BANK_TIMING
MC_CHANNEL_1_BANK_TIMING
MC_CHANNEL_2_BANK_TIMING
This register contains parameters that specify the bank timing parameters. These
values are in DCLK. The values in these registers are encoded where noted. All of these
values apply to commands to the same rank only.
Device:
Function: 0
Offset:
Access as a Dword
Bit
21:17
16:13
12:9
8:4
3:0
2.10.13
MC_CHANNEL_0_REFRESH_TIMING
MC_CHANNEL_1_REFRESH_TIMING
MC_CHANNEL_2_REFRESH_TIMING
This register contains parameters that specify the refresh timings. Units are in DCLK.
Device:
Function: 0
Offset:
Access as a Dword
Bit
29:19
18:9
8:0
70
4, 5, 6
88h
Reset
Type
Value
RW
0
tWTPr. Minimum Write CAS to Precharge command delay.
RW
0
tRTPr. Minimum Read CAS to Precharge command delay.
RW
0
tRCD. Minimum delay between Activate and CAS commands.
RW
0
tRAS. Minimum delay between Activate and Precharge commands.
RW
0
tRP. Minimum delay between Precharge command and Activate command.
4, 5, 6
8Ch
Reset
Type
Value
tTHROT_OPPREF.
The minimum time between two opportunistic refreshes. Should be set to tRFC in
DCLKS. Zero is an invalid encoding. A value of 1 should be programmed to disable
the throttling of opportunistic refreshes. By setting this field to tRFC, current to a
single DIMM can be limited to that required to support this scenario without
significant performance impact:
RW
0
• 8 panic refreshes in tREFI to one rank
• 1 opportunistic refresh every tRFC to another rank
• full bandwidth delivered by the third and fourth ranks
Platforms that can supply peak currents to the DIMMs should disable opportunistic
refresh throttling for max performance.
tREFI_8.
RW
0
Average periodic refresh interval divided by 8.
tRFC.
RW
0
Delay between the refresh command and an activate or refresh command.
Register Description
Description
Description
Datasheet
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