Mc_Channel_0_Ew_Bgf_Settings; Mc_Channel_1_Ew_Bgf_Settings; Mc_Channel_2_Ew_Bgf_Settings; Mc_Channel_0_Ew_Bgf_Offset_Settings - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

2.10.28

MC_CHANNEL_0_EW_BGF_SETTINGS

MC_CHANNEL_1_EW_BGF_SETTINGS

MC_CHANNEL_2_EW_BGF_SETTINGS

These are the parameters used to set the early warning RX clock crossing BGF.
Device:
Function: 0
Offset:
Access as a Dword
Bit
15:8
2.10.29

MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS

MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS

MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS

These are the parameters to set the early warning RX clock crossing BGF.
Device:
Function: 0
Offset:
Access as a Dword
Bit
15:8
7:0
2.10.30

MC_CHANNEL_0_ROUND_TRIP_LATENCY

MC_CHANNEL_1_ROUND_TRIP_LATENCY

MC_CHANNEL_2_ROUND_TRIP_LATENCY

These are the parameters to set the early warning RX clock crossing the Bubble
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
Device:
Function: 0
Offset:
Access as a Dword
Bit
7:0
78
4, 5, 6
CCh
Reset
Type
Value
RW 1 ALIENRATIO. Dclk to Bclk ratio. Early warning Alien Ratio setting.
4, 5, 6
D0h
Reset
Type
Value
RW 2 EVENOFFSET. Early warning even offset setting.
RW 0 ODDOFFSET. Early warning odd offset setting.
4, 5, 6
D4h
Reset
Type
Value
RW 0 ROUND_TRIP_LATENCY.
Round trip latency for reads. Units are in UCLK. This register must be
programmed with the appropriate time for read data to be retuned from the
pads after a READ CAS is sent to the DIMMs.
Register Description
Description
Description
Description
Datasheet