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2.10.10
MC_CHANNEL_0_RANK_TIMING_A
MC_CHANNEL_1_RANK_TIMING_A
MC_CHANNEL_2_RANK_TIMING_A
This register contains parameters that specify the rank timing used. All parameters are
in DCLK.
Device:
Function: 0
Offset:
Access as a Dword
Bit
28:26
25:23
22:19
66
4, 5, 6
80h
Reset
Type
Value
tddWrTRd.
Minimum delay between a write followed by a read to different DIMMs.
000 = 1
001 = 2
010 = 3
RW
0
011 = 4
100 = 5
101 = 6
110 = 7
111 = 8
tdrWrTRd.
Minimum delay between a write followed by a read to different ranks on the
same DIMM.
000 = 1
001 = 2
010 = 3
RW
0
011 = 4
100 = 5
101 = 6
110 = 7
111 = 8
tsrWrTRd.
Minimum delay between a write followed by a read to the same rank.
0000 = 10
0001 = 11
0010 = 12
0011 = 13
0100 = 14
RW
0
0101 = 15
0110 = 16
0111 = 17
1000 = 18
1001 = 19
1010 = 20
1011 = 21
1100 = 22
Register Description
Description
Datasheet
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