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2.10.6
MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT
This register supports Self Refresh and Thermal Throttle functions.
Device:
Function: 0
Offset:
Access as a Dword
Bit
3:2
1
0
2.10.7
MC_CHANNEL_0_MRS_VALUE_0_1
MC_CHANNEL_1_MRS_VALUE_0_1
MC_CHANNEL_2_MRS_VALUE_0_1
The initial MRS register values for MR0, and MR1 can be specified in this register. These
values are used for the automated MRS writes used as a part of the training FSM. The
remaining values of the MRS register must be specified here.
Device:
Function: 0
Offset:
Access as a Dword
Bit
31:16
15:0
64
4, 5, 6
68h
Reset
Type
Value
INC_ENTERPWRDWN_RATE.
Powerdown rate will be increased during thermal throttling based on the
following configurations.
00 = tRANKIDLE (Default)
RW
0
01 = 16
10 = 24
11 = 32
DIS_OP_REFRESH.
RW
0
When set, the refresh engine will not issue opportunistic refresh.
ASR_PRESENT.
When set, indicates DRAMs on this channel can support Automatic Self Refresh.
RW
0
If the DRAM is not supporting ASR (Auto Self Refresh), then Self Refresh entry
will be delayed until the temperature is below the 2x refresh temperature.
4, 5, 6
70h
Reset
Type
Value
MR1.
RW
0
The values to write to MR1 for A15:A0.
MR0.
RW
0
The values to write to MR0 for A15:A0.
Register Description
Description
Description
Datasheet
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