Mc_Channel_0_Scheduler_Params; Mc_Channel_1_Scheduler_Params; Mc_Channel_2_Scheduler_Params; Mc_Channel_0_Maintenance_Ops - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

2.10.24

MC_CHANNEL_0_SCHEDULER_PARAMS

MC_CHANNEL_1_SCHEDULER_PARAMS

MC_CHANNEL_2_SCHEDULER_PARAMS

These are the parameters used to control parameters within the scheduler.
Device:
Function: 0
Offset:
Access as a Dword
Bit
12
11
10:6
5
3
2:0
2.10.25

MC_CHANNEL_0_MAINTENANCE_OPS

MC_CHANNEL_1_MAINTENANCE_OPS

MC_CHANNEL_2_MAINTENANCE_OPS

This register enables various maintenance operations such as Refreshes, ZQ, RCOMP,
etc..
Device:
Function: 0
Offset:
Access as a Dword
Bit
12:0
76
4, 5, 6
B8h
Reset
Type
Value
CS_FOR_CKE_TRANSITION.
RW 1
Specifies if chip select is to be asserted when CKE transitions with PowerDown
entry/exit and SelfRefresh exit.
FLOAT_EN.
RW 0
When set, the address and command lines will float to save power when
commands are not being sent out. This setting may not work with RDIMMs.
PRECASRDTHRESHOLD.
RW 7
Threshold above which Medium-Low Priority reads can PRE-CAS write requests.
DISABLE_ISOC_RBC_RESERVE.
RW 0
When set this bit will prevent any RBC's from being reserved for ISOC.
RW 0 ENABLE2N. Enable 2n Timing.
PRIORITYCOUNTER.
RW 0
Upper 3 MSB of 8 bit priority time out counter.
4, 5, 6
BCh
Reset
Type
Value
MAINT_CNTR.
RW 0
Value to be loaded in the maintenance counter. This counter sequences the rate
to Refreshes, ZQ, RCOMP.
Register Description
Description
Description
Datasheet