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2.9.2
TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7................................58
2.10
Integrated Memory Controller Channel Control Registers.........................................59
2.10.1
MC_CHANNEL_2_DIMM_RESET_CMD .......................................................59
2.10.2
MC_CHANNEL_2_DIMM_INIT_CMD ..........................................................60
2.10.3
MC_CHANNEL_2_DIMM_INIT_PARAMS .....................................................61
2.10.4
MC_CHANNEL_2_DIMM_INIT_STATUS .....................................................62
2.10.5
MC_CHANNEL_2_DDR3CMD....................................................................63
2.10.6
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT ......................................64
2.10.7
MC_CHANNEL_2_MRS_VALUE_0_1 ..........................................................64
2.10.8
MC_CHANNEL_2_MRS_VALUE_2 .............................................................65
2.10.9
MC_CHANNEL_2_RANK_PRESENT............................................................65
MC_CHANNEL_2_RANK_TIMING_A ..........................................................66
MC_CHANNEL_2_RANK_TIMING_B ..........................................................69
MC_CHANNEL_2_BANK_TIMING ..............................................................70
MC_CHANNEL_2_REFRESH_TIMING.........................................................70
MC_CHANNEL_2_CKE_TIMING ................................................................71
MC_CHANNEL_1_ZQ_TIMING
MC_CHANNEL_2_ZQ_TIMING .................................................................71
MC_CHANNEL_2_RCOMP_PARAMS...........................................................72
MC_CHANNEL_2_ODT_PARAMS1.............................................................72
MC_CHANNEL_2_ODT_PARAMS2.............................................................73
4
Datasheet
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