Mc_Tx_Bg_Cmd_Data_Ratio_Settings_Ch2; Mc_Tx_Bg_Cmd_Offset_Settings_Ch0; Mc_Tx_Bg_Cmd_Offset_Settings_Ch1; Mc_Tx_Bg_Cmd_Offset_Settings_Ch2 - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1

MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2

Channel Bubble Generator ratios for CMD and DATA.
Device:
Function: 0
Offset:
Access as a Dword
Bit
15:8
7:0
2.10.34

MC_TX_BG_CMD_OFFSET_SETTINGS_CH0

MC_TX_BG_CMD_OFFSET_SETTINGS_CH1

MC_TX_BG_CMD_OFFSET_SETTINGS_CH2

Integrated Memory Controller Channel Bubble Generator Offsets for CMD FIFO. The
Data command FIFOs share the settings for channel 0 across all three channels. The
register in Channel 0 must be programmed for all configurations.
Device:
Function: 0
Offset:
Access as a Dword
Bit
9:8
7:0
2.10.35

MC_TX_BG_DATA_OFFSET_SETTINGS_CH0

MC_TX_BG_DATA_OFFSET_SETTINGS_CH1

MC_TX_BG_DATA_OFFSET_SETTINGS_CH2

Integrated Memory Controller Channel Bubble Generator Offsets for DATA FIFO.
Device:
Function: 0
Offset:
Access as a Dword
Bit
16:14
13:10
9:8
7:0
80
4, 5, 6
E0h
Reset
Type
Value
RW 1 ALIENRATIO. DCLK to BCLK ratio.
RW 4 NATIVERATIO. UCLK to BCLK ratio.
4, 5, 6
E4h
Reset
Type
Value
RW 0 PTROFFSET. FIFO pointer offset.
RW 0 BGOFFSET. BG offset.
4, 5, 6
E8h
Reset
Type
Value
RW 0 RDPTROFFSET. Read FIFO pointer offset.
RW 0 WRTPTROFFSET. Write FIFO pointer offset.
RW 0 PTROFFSET. FIFO pointer offset.
RW 0 BGOFFSET. BG offset.
Register Description
Description
Description
Description
Datasheet