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CS-series Instruction Execution Times and Number of Steps
Instruction
Mnemonic
CONDI-
EXIT (bit
TIONAL
address)
BLOCK
EXIT
CONDI-
EXIT NOT
TIONAL
(bit address)
BLOCK
EXIT (NOT)
Branching
IF (execution
condition)
Branching
IF (relay
number)
Branching
IF NOT
(NOT)
(relay num-
ber)
Branching
ELSE
Branching
IEND
ONE
WAIT (exe-
CYCLE AND
cution condi-
WAIT
tion)
ONE
WAIT (relay
CYCLE AND
number)
WAIT
ONE
WAIT NOT
CYCLE AND
(relay num-
WAIT (NOT)
ber)
COUNTER
CNTW
WAIT
CNTWX
TEN-MS
TMHW
TIMER
WAIT
TMHWX
Loop Control LOOP
Loop Control LEND (exe-
cution condi-
tion)
Code
Length
(steps)
CPU-6@H CPU-4@H
(See note.)
806
2
6.8
4.7
806
2
12.4
7.1
802
1
4.6
6.7
802
2
6.8
9.0
802
2
7.1
9.2
803
1
6.2
6.8
804
1
6.9
4.4
805
1
12.6
3.9
805
2
12.0
6.1
805
2
12.2
6.4
814
4
17.9
19.1
818
4
17.9
19.1
815
3
25.8
20.6
817
3
25.8
20.6
9.3
809
1
7.9
810
1
7.7
6.8
ON execution time ( s)
CPU-6@
CPU-4@
13.5
16.3
16.3
7.2
10.7
10.7
14.0
16.8
16.8
7.6
11.2
11.2
4.8
7.2
7.2
7.3
10.9
10.9
7.2
10.4
10.4
9.6
14.2
14.2
7.6
10.9
10.9
10.1
14.7
14.7
6.7
9.9
9.9
7.7
11.2
11.2
7.7
11.0
11.0
4.6
7.0
7.0
13.7
16.7
16.7
4.1
6.3
6.3
13.4
16.5
16.5
6.5
9.6
9.6
13.8
17.0
17.0
6.9
10.1
10.1
22.6
27.4
27.4
23.9
28.7
28.7
22.6
---
---
23.9
---
---
27.9
34.1
34.1
22.7
28.9
28.9
27.9
---
---
22.7
---
---
10.8
---
---
9.1
12.3
12.3
8.4
10.9
10.9
8.0
9.8
9.8
Section 4-1
Conditions
EXIT condition
satisfied
EXIT condition
not satisfied
EXIT condition
satisfied
EXIT condition
not satisfied
IF true
IF false
IF true
IF false
IF true
IF false
IF true
IF false
IF true
IF false
WAIT condition
satisfied
WAIT condition
not satisfied
WAIT condition
satisfied
WAIT condition
not satisfied
WAIT condition
satisfied
WAIT condition
not satisfied
Default setting
Normal execu-
tion
Default setting
Normal execu-
tion
Default setting
Normal execu-
tion
Default setting
Normal execu-
tion
LEND condition
not satisfied
---
LEND condition
satisfied
LEND condition
not satisfied
1309
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