Omron SYSMAC CJ - REFERENCE MANUAL 08-2008 Reference Manual page 1332

CS-series Instruction Execution Times and Number of Steps
Instruction Mnemonic
SHIFT N-BIT NSFR
DATA RIGHT
SHIFT N-BITS NASL
LEFT
DOUBLE NSLL
SHIFT N-BITS
LEFT
SHIFT N-BITS NASR
RIGHT
DOUBLE NSRL
SHIFT N-BITS
RIGHT
4-1-8 Increment/Decrement Instructions
Instruction Mnemonic
INCREMENT ++
BINARY
DOUBLE ++L
INCREMENT
BINARY
DECREMENT – –
BINARY
DOUBLE DEC- – –L
REMENT
BINARY
INCREMENT ++B
BCD
DOUBLE ++BL
INCREMENT
BCD
DECREMENT – –B
BCD
DOUBLE DEC- – –BL
REMENT BCD
1292
Code Length
(steps)
(See note.)
579 4
580 3
582 3
581 3
583 3
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Code Length
(steps)
(See note.)
590 2
591 2
592 2
593 2
594 2
595 2
596 2
597 2
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
ON execution time ( s)
CPU-6@H CPU-4@H CPU-6@
7.5 8.3 10.5
50.5 55.3 69.3
0.22 0.32 0.29
0.40 0.56 0.50
0.22 0.32 0.29
0.40 0.56 0.50
ON execution time ( s)
CPU-6@H CPU-4@H CPU-6@
0.22 0.32 0.29
0.40 0.56 0.50
0.22 0.32 0.29
0.40 0.56 0.50
6.4 4.5 7.4
5.6 4.9 6.1
6.3 4.6 7.2
5.3 4.7 7.1
Section 4-1
Conditions
CPU-4@
10.5 Shifting 1 bit
69.3 Shifting 1,000
bits
0.37 ---
0.67 ---
0.37 ---
0.67 ---
Conditions
CPU-4@
0.37 ---
0.67 ---
0.37 ---
0.67 ---
7.4 ---
6.1 ---
7.2 ---
7.1 ---