Omron CJ - PROGRAMMING MANUAL 12-2009 Programming Manual page 235

Interrupt Tasks
Programming
Console
address
Word +128, Interrupt Task Error
bit 14 Detection
Related Auxiliary Area Flags/Words
Name
Interrupt Task Error A40213
Flag
Interrupt Task Error, A426
Task Number
Disabling Interrupts
Data Concurrency
between Cyclic and
Interrupt Tasks
The following table shows the corresponding settings when using a Program-
ming Console.
Name
Specifies whether or not to detect interrupt
task errors. The Interrupt Task Error Flag
(A40213) will be function when detection is
enabled.
Address
Turns ON if an interrupt task executes for more than 10 ms during
C200H Special I/O Unit or SYSMAC BUS Remote I/O refresh, but the
CPU Unit will continue running. The ERR/ALM LED will light on the
front panel (CS Series only).
Also turns ON if Interrupt Task Error Detection is enabled for a Special
I/O Unit in the PLC Setup, and one of the following conditions occurs for
that Special I/O Unit.
• There is a conflict between an IORF, FIORF (CJ1-H-R only), IORD,
or IOWR instruction executed in the interrupt task and an IORF,
FIORF (CJ1-H-R only), IORD, or IOWR instruction executed in the
cyclic task.
• There is a conflict between an IORF, FIORF (CJ1-H-R only), IORD,
or IOWR instruction executed in the interrupt task and the CPU
Unit's I/O refreshing (END refreshing).
Note When a Special I/O Unit's Cyclic Refreshing is enabled in the PLC Setup,
Contains the interrupt task number or the number of the Special I/O
Unit being refreshed.
(Bit 15 will be OFF when execution of an interrupt task requires 10 ms
or longer and ON when duplicated Special I/O Unit refreshing has
occurred.)
Processing will be interrupted and the interrupt task will be executed in the fol-
lowing instances.
• While an instruction is being executed
• During Basic I/O Unit, CPU Bus Unit, Inner Board (CS Series only), or
SYSMAC BUS remote I/O (CS Series only) refreshing
• During HOST LINK servicing
Data may not be concurrent if a cyclic (including extra cyclic tasks) and an
interrupt task are reading and writing the same I/O memory addresses. Use
the following procedure to disable interrupts during memory access by cyclic
task instructions.
• Immediately prior to reading or writing by a cyclic task instruction, use a
DI (DISABLE INTERRUPT) instruction to disable execution of interrupt
tasks.
• Use an EI (ENABLE INTERRUPT) instruction immediately after process-
ing in order to enable interrupt task execution.
Description
Description
and an IORF, FIORF (CJ1-H-R only), IORD, or IOWR instruction is exe-
cuted for the same Special I/O Unit, there will be duplicate refreshing and
an Interrupt Task Error will occur.
Section 4-3
Settings Default
setting
0: Detection 0
enabled,
1: Detection
disabled
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