Connecting The Sample Clock - HP 3563A Operating Manual

Connecti ng the Sample Clock
The analyzer clocks data from both channels into internal memory with the sample clock. See
figure 13-19. The sample clock is chosen from among the various clock signal inputs. The sample
clock can be either Pod Q Clock, External Sample, Channel 1 clock, or Channel 2 clock. The
frequency range of the sample clock is 0.001 Hz to 256 kHz. If the signal selected for the sample
clock is not present or occurs at a rate that is slower than the qualified data clocks, the message
"MISSED SAMPLE Check External Clock" appears in the lower-right corner of the display.
1 5
I
0 0 - 0
Pod
2
data
clock
data
[ "
Po d
00-Q7
Q
EXT
{clock)
SAMPLE
Note
No measurement activity occurs when there is no sample clock. If you start a
measurement and nothing seems to happen, look for the MISSED SAMPLE
message in the lower-right corner of the display.
Chan
multiplexer
and latch
Chan
2
Charl 1 clock
Qualifier
Sample
Chan clock
logic
Source Enable
(Does not illustrate use of 16-bit data on an 8-bit bus.)
Figure 13-19. Clock Signals in the Block Diagram
2
1
multiplexer
latch
and latch
Digital
sample
clock
logic
Source
part of Pod
ulgltal (.;onnectlons

Connecting the Sample Clock

Channel
2
measurement data
Pod LSB
Pod MSB
(rear panel)
X
SRC-EN
(for tri-state buffer)
13-19