Connecting The Qualifier Pod; Clock Qualifiers - HP 3563A Operating Manual

Digital Connections
Connecting the Qualifier
Co nnecting the Qualifier Pod

Clock Qualifiers

In some applications, data isn't valid at every transition of the data clock signal. In such cases, you
can use the eight qualifier lines on Pod
analyzer monitors the state of the qualifier lines
When the selected clock edge occurs and the qualifier signal states match the user-specified qualifier
pattern, data is latched into the Ch
CLOCK QUALFR?
defined with the
Note
The clock on Pod
The data rate of the qualified data clock (channel clock) must not exceed
The data clock, itself, may run much faster_
Example
In figure 13-13 a microprocessor generates a digital signal which is written to a DAC
(digital-to-analog converter) connected to the microprocessor bus. The data is transferred using a
write pulse (WR) in conjunction with an address. To read the same data with the
WR signal is connected to the CLK input on Pod
address lines are connected to
is
qualified data clock called a
qualifier signal states match a user-specified pattern. Note that this configuration offers access to
another channel of data by specifying another qualifier pattern for Channel
2.
Pod
See figure 13-11 for setup and hold times relative to the data clock. See "Data Size" on page
for more detail.
HP 3563A
1 3-14
Pod
0 (0D-07)
1/2 data latches shown in figure
data-entry softkey as described in chapter
Q
cannot be qualified.
QO- Q7 on Pod
The data clock generates a channel clock when the
channel clock.
Pod
1
. Figure 13-13. Example of Qualifier Selection
to qualify data clocked into the analyzer. The
QD-Q7, comparing them to states you specify.
13-19.
1. This signal serves as the data clock. The
Q. These serve to qualify the data clock. The
data bus
DAC
address bus
WR
microprocessor
The qualifier pattern is
7.
256 kHz
HP 3563A, the
2; without connecting
13-12
analog
output
.